Everything you need to know about 80386 microprocessor

80386 Microprocessor

The salient features:

• 8, 16, 32-Bit Data Types
• 8 General Purpose 32-Bit Registers
• Very Large Address Space
• 4 Gigabyte Physical
• 64 Terabyte Virtual
• 4 Gigabyte Maximum Segment Size
• Integrated Memory Management Unit
• Virtual Memory Support
• Optional On-Chip Paging
• 4 Levels of Protection
• Fully Compatible with 80286
• Object Code Compatible with All 8086 Family Microprocessors
• Virtual 8086 Mode Allows Running of 8086 Software in a Protected and Paged System
• Hardware Debugging Support
• Optimized for System Performance
• Pipelined Instruction Execution
• On-Chip Address Translation Caches
• 20, 25 and 33 MHz Clock
• 40, 50 and 66 Megabytes/Sec Bus Bandwidth
• Numerics Support via Intel i387 DX Math Coprocessor
• Complete System Development Support
• Software: C, PL/M, Assembler
• System Generation Tools
• Debuggers: PSCOPE, ICETM-386
• High Speed CHMOS IV Technology
• 132 Pin Grid Array Package
• 132 Pin Plastic Quad Flat Package

More about 80386 microprocessor: 

The 80386 is an advanced 32-bit microprocessor optimized for multitasking operating systems and designed for applications needing very high performance. The 32-bit registers and data paths support 32-bit addresses and data types. The processor can address up to four gigabytes of physical memory and 64 terabytes (246 bytes) of virtual memory. The on-chip memory-management facilities include address translation registers, advanced multitasking hardware, a protection mechanism, and paged virtual memory. Special debugging registers provide data and code breakpoints even in ROM-based software.

The distinction between applications features and systems features is determined by the protection mechanism of the 80386. One purpose of protection is to prevent applications from interfering with the operating system; therefore, the processor makes certain registers and instructions inaccessible to applications programs.

The processing mode of the 80386 also determines the features that are accessible. The 80386 has three processing modes

1. Protected Mode.
2. Real-Address Mode.
3. Virtual 8086 Mode.

Protected mode is the natural 32-bit environment of the 80386 processor. In this mode all instructions and features are available. Real-address mode (often called just "real mode") is the mode of the processor immediately after RESET. In real mode the 80386 appears to programmers as a fast 8086 with some new instructions. Most applications of the 80386 will use real mode for initialization only.

Virtual 8086 mode (also called V86 mode) is a dynamic mode in the sense that the processor can switch repeatedly and rapidly between V86 mode and protected mode. The CPU enters V86 mode from protected mode to execute an 8086 program, then leaves V86 mode and enters protected mode to continue executing a native 80386 program.

The features that are available to applications programs in protected mode and to all programs in V86 mode are the same.

To know more watch this video

Lets know depper about 80386.........

Architecture of 80386:

•The Internal Architecture of 80386 is divided into 3 sections.
 •Central processing unit
•Memory management unit
•Bus interface unit
•Central processing unit is further divided into Execution unit and Instruction unit
•Execution unit has 8 General purpose and 8 Special purpose registers which are either used for handling data or calculating offset addresses.

•The Instruction unit decodes the opcode bytes received from the 16-byte instruction code queue and arranges them in a 3- instruction decoded instruction queue. 

•After decoding them pass it to the control section for deriving the necessary control signals. The barrel shifter increases the speed of all shift and rotate operations. 

• The multiply / divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum time.

•Even 32- bit multiplications can be executed within one microsecond by the multiply / divide logic. •The Memory management unit consists of a Segmentation unit and a Paging unit. 

•Segmentation unit allows the use of two address components, viz. segment and offset for reliability and sharing of code and data. 

•Segmentation unit allows segments of size 4Gbytes at max. •The Paging unit organizes the physical memory in terms of pages of 4k bytes size each. 

•Paging unit works under the control of the segmentation unit, i.e. each segment is further divided into pages. The virtual memory is also organizes in terms of segments and pages by the memory management unit. 

•The Segmentation unit provides a 4 level protection mechanism for protecting and isolating the system code and data from those of the application program. 

•Paging unit converts linear addresses into physical addresses. 

•The control and attribute PLA checks the privileges at the page level. Each of the pages maintains the paging information of the task. The limit and attribute PLA checks segment limits and attributes at segment level to avoid invalid accesses to code and data in the memory segments. 

•The Bus control unit has a prioritizer to resolve the priority of the various bus requests. This controls the access of the bus. The address driver drives the bus enable and address signal A0 – A31. The pipeline and dynamic bus sizing unit handle the related control signals. 

•The data buffers interface the internal data bus with the system bus. 

PIN DIAGRAM:

captured from my book

Signal Descriptions of 80386:

 •CLK2 :The input pin provides the basic system clock timing for the operation of 80386. 

•D0 – D31:These 32 lines act as bidirectional data bus during different access cycles. 

•A31 – A2: These are upper 30 bit of the 32- bit address bus. 

• BE 0 toBE3 : The 32- bit data bus supported by 80386 and the memory system of 80386 can be viewed as a 4- byte wide memory access mechanism. The 4 byte enable lines BE 0 to BE3 , may be used for enabling these 4 blanks. Using these 4 enable signal lines, the CPU may transfer 1 byte / 2 / 3 / 4 byte of data simultaneously. 

•ADS#: The address status output pin indicates that the address bus and bus cycle definition pins( W/R#, D/C#, M/IO#, BE0# to BE3# ) are carrying the respective valid signals. The 80383 does not have any ALE signals and so this signals may be used for latching the address to external latches. 

•READY#: The ready signals indicates to the CPU that the previous bus cycle has been terminated and the bus is ready for the next cycle. The signal is used to insert WAIT states in a bus cycle and is useful for interfacing of slow devices with CPU. 

•VCC: These are system power supply lines. 

•VSS: These return lines for the power supply. 

•BS16#: The bus size – 16 input pin allows the interfacing of 16 bit devices with the 32 bit wide 80386 data bus. Successive 16 bit bus cycles may be executed to read a 32 bit data from a peripheral. 

•HOLD: The bus hold input pin enables the other bus masters to gain control of the system bus if it is asserted. 

•HLDA: The bus hold acknowledge output indicates that a valid bus hold request has been received and the bus has been relinquished by the CPU. 

•BUSY#: The busy input signal indicates to the CPU that the coprocessor is busy with the allocated task. 

•ERROR#: The error input pin indicates to the CPU that the coprocessor has encountered an error while executing its instruction. 

•PEREQ: The processor extension request output signal indicates to the CPU to fetch a data word for the coprocessor. 

•INTR: This interrupt pin is a maskable interrupt, that can be masked using the IF of the flag register. 

•NMI: A valid request signal at the non-maskable interrupt request input pin internally generates a non- maskable interrupt of type 2. 

•RESET: A high at this input pin suspends the current operation and restart the execution from the starting location. 

•N / C : No connection pins are expected to be left open while connecting the 80386 in the circuit.

Register Organisation: 

•The 80386 has eight 32 - bit general purpose registers which may be used as either 8 bit or 16 bit registers.
•A 32 - bit register known as an extended register, is represented by the register name with prefix E.
•Example : A 32 bit register corresponding to AX is EAX, similarly BX is EBX etc.
•The 16 bit registers BP, SP, SI and DI in 8086 are now available with their extended size of 32 bit and are names as EBP,ESP,ESI and EDI.
•AX represents the lower 16 bit of the 32 bit register EAX. • BP, SP, SI, DI represents the lower 16 bit of their 32 bit counterparts, and can be used as independent 16 bit registers.
•The six segment registers available in 80386 are CS, SS, DS, ES, FS and GS.
•The CS and SS are the code and the stack segment registers respectively, while DS, ES, FS, GS are 4 data segment registers.
•A 16 bit instruction pointer IP is available along with 32 bit counterpart EIP. 

•Flag Register of 80386: The Flag register of 80386 is a 32 bit register. Out of the 32 bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is always set at 1.Two extra new flags are added to the 80286 flag to derive the flag register of 80386. They are VM and RF flags. 

•VM - Virtual Mode Flag: If this flag is set, the 80386 enters the virtual 8086 mode within the protection mode. This is to be set only when the 80386 is in protected mode. In this mode, if any privileged instruction is executed an exception 13 is generated. This bit can be set using IRET instruction or any task switch operation only in the protected mode.

•RF- Resume Flag: This flag is used with the debug register breakpoints. It is checked at the starting of every instruction cycle and if it is set, any debug fault is ignored during the instruction cycle. The RF is automatically reset after successful execution of every instruction, except for IRET and POPF instructions. 

•Also, it is not automatically cleared after the successful execution of JMP, CALL and INT instruction causing a task switch. These instruction are used to set the RF to the value specified by the memory data available at the stack. 

•Segment Descriptor Registers: This registers are not available for programmers, rather they are internally used to store the descriptor information, like attributes, limit and base addresses of segments. 

•The six segment registers have corresponding six 73 bit descriptor registers. Each of them contains 32 bit base address, 32 bit base limit and 9 bit attributes. These are automatically loaded when the corresponding segments are loaded with selectors. 

•Control Registers: The 80386 has three 32 bit control registers CR0, CR2 and CR3 to hold global machine status independent of the executed task. Load and store instructions are available to access these registers. 

•System Address Registers: Four special registers are defined to refer to the descriptor tables supported by 80386. 

•The 80386 supports four types of descriptor table, viz. global descriptor table (GDT), interrupt descriptor table (IDT), local descriptor table (LDT) and task state segment descriptor (TSS). 

•Debug and Test Registers: Intel has provide a set of 8 debug registers for hardware debugging. Out of these eight registers DR0 to DR7, two registers DR4 and DR5 are Intel reserved. 

•The initial four registers DR0 to DR3 store four program controllable breakpoint addresses, while DR6 and DR7 respectively hold breakpoint status and breakpoint control information. 

•Two more test register are provided by 80386 for page caching namely test control and test status register. 

•ADDRESSING MODES: The 80386 supports overall eleven addressing modes to facilitate efficient execution of higher level language programs. 

•In case of all those modes, the 80386 can now have 32-bit immediate or 32- bit register operands or displacements. 

•The 80386 has a family of scaled modes. In case of scaled modes, any of the index register values can be multiplied by a valid scale factor to obtain the displacement.

 •The valid scale factor are 1, 2, 4 and 8. 

•The different scaled modes are as follows. 

•Scaled Indexed Mode: Contents of the an index register are multiplied by a scale factor that may be added further to get the operand offset. 

•Based Scaled Indexed Mode: Contents of the an index register are multiplied by a scale factor and then added to base register to obtain the offset. 

•Based Scaled Indexed Mode with Displacement: The Contents of the an index register are multiplied by a scaling factor and the result is added to a base register and a displacement to get the offset of an operand. 

Real Address Mode of 80386 

•After reset, the 80386 starts from memory location FFFFFFF0H under the real address mode. In the real mode, 80386 works as a fast 8086 with 32-bit registers and data types. 

•In real mode, the default operand size is 16 bit but 32- bit operands and addressing modes may be used with the help of override prefixes. 

•The segment size in real mode is 64k, hence the 32-bit effective addressing must be less than 0000FFFFFH. The real mode initializes the 80386 and prepares it for protected mode. 

•Memory Addressing in Real Mode: In the real mode, the 80386 can address at the most

1Mbytes of physical memory using address lines A0-A19.

•Paging unit is disabled in real addressing mode, and hence the real addresses are the

same as the physical addresses.

•To form a physical memory address, appropriate segment registers contents (16-bits) are

shifted left by four positions and then added to the 16-bit offset address formed using one

of the addressing modes, in the same way as in the 80386 real address mode.

•The segment in 80386 real mode can be read, write or executed, i.e. no protection is

available.

•Any fetch or access past the end of the segment limit generate exception 13 in real

address mode.

•The segments in 80386 real mode may be overlapped or non-overlapped.

•The interrupt vector table of 80386 has been allocated 1Kbyte space starting from

00000H to 003FFH.

Protected Mode of 80386:

•All the capabilities of 80386 are available for utilization in its protected mode of

operation.

•The 80386 in protected mode support all the software written for 80286 and 8086 to be

executed under the control of memory management and protection abilities of 80386.

•The protected mode allows the use of additional instruction, addressing modes and

capabilities of 80386. 

•ADDRESSING IN PROTECTED MODE: 

In this mode, the contents of segment registers are used as selectors to address descriptors which contain the segment limit,

base address and access rights byte of the segment.

•The effective address (offset) is added with segment base address to calculate linear

address. This linear address is further used as physical address, if the paging unit is

disabled, otherwise the paging unit converts the linear address into physical address.

•The paging unit is a memory management unit enabled only in protected mode. The

paging mechanism allows handling of large segments of memory in terms of pages of

4Kbyte size.

•The paging unit operates under the control of segmentation unit. The paging unit if

enabled converts linear addresses into physical address, in protected mode. 

Segmentation:

•DESCRIPTOR TABLES: These descriptor tables and registers are manipulated by the

operating system to ensure the correct operation of the processor, and hence the correct

execution of the program.

•Three types of the 80386 descriptor tables are listed as follows:

•GLOBAL DESCRIPTOR TABLE ( GDT )

•LOCAL DESCRIPTOR TABLE ( LDT )

•INTERRUPT DESCRIPTOR TABLE ( IDT )

•DESCRIPTORS: The 80386 descriptors have a 20-bit segment limit and 32-bit segment

address. The descriptor of 80386 are 8-byte quantities access right or attribute bits along

with the base and limit of the segments.

•Descriptor Attribute Bits: The A (accessed) attributed bit indicates whether the segment

has been accessed by the CPU or not.

•The TYPE field decides the descriptor type and hence the segment type.

•The S bit decides whether it is a system descriptor (S=0) or code/data segment descriptor

( S=1).

•The DPL field specifies the descriptor privilege level.

•The D bit specifies the code segment operation size. If D=1, the segment is a 32-bit

operand segment, else, it is a 16-bit operand segment.

•The P bit (present) signifies whether the segment is present in the physical memory or

not. If P=1, the segment is present in the physical memory.

•The G (granularity) bit indicates whether the segment is page addressable. The zero bit

must remain zero for compatibility with future process.

•The AVL (available) field specifies whether the descriptor is for user or for operating

system.

•The 80386 has five types of descriptors listed as follows:

1.Code or Data Segment Descriptors.

2.System Descriptors.

3.Local descriptors.

4.TSS (Task State Segment) Descriptors.

5.GATE Descriptors.

•The 80386 provides a four level protection mechanism exactly in the same way as the

80286 does. 

Paging:

•PAGING OPERATION: Paging is one of the memory management techniques used for

virtual memory multitasking operating system.

•The segmentation scheme may divide the physical memory into a variable size segments

but the paging divides the memory into a fixed size pages.

•The segments are supposed to be the logical segments of the program, but the pages do

not have any logical relation with the program.

•The pages are just fixed size portions of the program module or data.

•The advantage of paging scheme is that the complete segment of a task need not be in

the physical memory at any time.

•Only a few pages of the segments, which are required currently for the execution need to

be available in the physical memory. Thus the memory requirement of the task is

substantially reduced, relinquishing the available memory for other tasks.

•Whenever the other pages of task are required for execution, they may be fetched from

the secondary storage.

•The previous page which are executed, need not be available in the memory, and hence

the space occupied by them may be relinquished for other tasks.

•Thus paging mechanism provides an effective technique to manage the physical memory

for multitasking systems. 

•Paging Unit: The paging unit of 80386 uses a two level table mechanism to convert a

linear address provided by segmentation unit into physical addresses.

•The paging unit converts the complete map of a task into pages, each of size 4K. The

task is further handled in terms of its page, rather than segments.

•The paging unit handles every task in terms of three components namely page directory,

page tables and page itself.

•Paging Descriptor Base Register: The control register CR2 is used to store the 32-bit

linear address at which the previous page fault was detected.

•The CR3 is used as page directory physical base address register, to store the physical

starting address of the page directory.

•The lower 12 bit of the CR3 are always zero to ensure the page size aligned directory. A

move operation to CR3 automatically loads the page table entry caches and a task switch

operation, to load CR0 suitably.

•Page Directory : This is at the most 4Kbytes in size. Each directory entry is of 4 bytes,

thus a total of 1024 entries are allowed in a directory.

•The upper 10 bits of the linear address are used as an index to the corresponding page

directory entry. The page directory entries point to page tables.

•Page Tables: Each page table is of 4Kbytes in size and many contain a maximum of

1024 entries. The page table entries contain the starting address of the page and the

statistical information about the page.

•The upper 20 bit page frame address is combined with the lower 12 bit of the linear

address. The address bits A12- A21 are used to select the 1024 page table entries. The page

table can be shared between the tasks.

•The P bit of the above entries indicate, if the entry can be used in address translation.

•If P=1, the entry can be used in address translation, otherwise it cannot be used.

•The P bit of the currently executed page is always high.

•The accessed bit A is set by 80386 before any access to the page. If A=1, the page is

accessed, else unaccessed.

•The D bit ( Dirty bit) is set before a write operation to the page is carried out. The D-bit

is undefined for page director entries.

•The OS reserved bits are defined by the operating system software.

•The User / Supervisor (U/S) bit and read/write bit are used to provide protection. These

bits are decoded to provide protection under the 4 level protection model.

•The level 0 is supposed to have the highest privilege, while the level 3 is supposed to

have the least privilege.

•This protection provide by the paging unit is transparent to the segmentation unit. 

 

will be conitinued........